?1 cxk5t8257btm/bym/bm -10llx/12llx pe96509-st 32768-word 8-bit high speed cmos static ram description the cxk5t8257btm/bym/bm is 262,144 bits high speed cmos static ram organized as 32768-words by 8 bits. special feature are low power consumption and high speed. the cxk5t8257btm/bym/bm is a suitable ram for portable equipment with battery back up. features extended operating temperature range: ?5 to +85? wide supply voltage range operation: 2.7 to 3.6v fast access time: (access time) 3.0v operation -10llx 100ns (max.) -12llx 120ns (max.) 3.3v operation -10llx 85ns (max.) -12llx 100ns (max.) low standby current: 7.0 a (max.) low power data retention: 2.0v (min.) available in many packages cxk5t8257btm/bym 8mm 13.4mm 28 pin tsop package cxk5t8257bm 450mil 28 pin sop package function 32768-word 8 bit static ram structure silicon gate cmos ic sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. cxk5t8257btm 28 pin tsop (plastic) cxk5t8257bym 28 pin tsop (plastic) cxk5t8257bm 28 pin sop (plastic) memory matrix 512 512 i/o gate column decoder row decoder buffer buffer buffer i/o buffer v cc gnd i/o1 i/o8 a14 a13 a12 a11 a9 a8 a7 a6 a5 a10 a4 a3 a2 a1 a0 oe we ce block diagram preliminary
?2 cxk5t8257btm/bym/bm 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 v cc we a13 a8 a9 a11 oe a10 ce i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 a4 a5 a6 a7 a12 a14 cxk5t8257bm a11 a9 a8 a13 we v cc a14 a12 a7 a6 a5 a4 oe a10 ce i/o8 i/o7 i/o6 i/o5 i/o4 gnd i/o3 i/o2 i/o1 a0 a1 a2 a3 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 cxk5t8257btm (standard pinout) a4 a5 a6 a7 a12 a14 v cc we a13 a8 a9 a11 a3 a2 a1 a0 i/o1 i/o2 i/o3 gnd i/o4 i/o5 i/o6 i/o7 i/o8 ce a10 oe 7 6 5 4 3 2 1 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 cxk5t8257bym (standard pinout) address input data input/output chip enable input write enable input output enable input power supply ground a0 to a14 i/o1 to i/o8 ce we oe v cc gnd symbol description pin description pin configuration (top view) supply voltage input voltage input and output voltage allowable power dissipation operating temperature storage temperature soldering temperature ?time v cc v in v i/o p d topr tstg tsolder ?.5 to +4.6 ?.5 * 1 to v cc + 0.5 ?.5 * 1 to v cc + 0.5 0.7 ?5 to +85 ?5 to +150 235 ?10 v v v w ? ? ? ?s item symbol rating unit h l l l h l h h l not selected output disable read write high z high z data out data in i sb1 , i sb2 i cc1 , i cc2 i cc1 , i cc2 i cc1 , i cc2 ce oe we mode i/o1 to i/o8 v cc current absolute maximum ratings (ta = 25?, gnd = 0v) * 1 v in , v i/o = ?.0v min. for pulse width less than 50ns. truth table : "h" or "l"
?3 cxk5t8257btm/bym/bm electrical characteristics dc characteristics (v cc = 2.7 to 3.6v, gnd = 0v, ta = ?5 to +85?) item symbol test conditions min. typ. * 2 max. unit input leakage current output leakage current operating power supply current average operating current standby current output high voltage output low voltage i li i lo i cc1 i cc2 i sb1 i sb2 v oh v ol v in = gnd to v cc ce = v ih oe = v ih or we = v il v i/o = gnd to v cc ce = v il v in = v ih or v il i out = 0ma min. cycle duty = 100%, i out = 0ma ce 3 v cc ?0.2v ce = v ih i oh = ?ma i ol = 2.0ma ?.5 ?.5 2.4 0.5 0.5 2 35 * 4 35 7.0 3.5 0.7 0.4 0.9 18 * 3 18 0.12 0.06 ? ma ? ma v * 2 v cc = 3.3v, ta = 25? * 3 i cc2 = 21ma for 3.3v operation (v cc = 3.3v 0.3v) * 4 i cc3 = 40ma for 3.3v operation (v cc = 3.3v 0.3v) 10llx 12llx ?5 to +85? ?5 to +70? +25? dc recommended operating conditions (ta = ?5 to +85?, gnd = 0v) * 1 v il =?.0v min. for pulse width less than 50ns. supply voltage input high voltage input low voltage item symbol min. v cc = 2.7 to 3.6v v cc = 3.3v 0.3v typ. max. unit v cc v ih v il 2.7 2.4 ?.3 * 1 3.3 3.6 v cc + 0.3 0.4 min. typ. max. 3.0 2.2 ?.3 * 1 3.3 3.6 v cc + 0.3 0.6 v
?4 cxk5t8257btm/bym/bm input capacitance i/o capacitance item symbol test condition min. typ. max. unit c in c i/o 8 10 pf pf v in = 0v v i/o = 0v ttl c l ac characteristics ac test conditions (ta = ?5 to +85?) * 1 c l includes scope and jig capacitances. i/o capacitance (ta = 25?, f = 1mhz) note) this parameter is sampled and is not 100% tested. input pulse high level input pulse low level input rise time input fall time input and output reference level output load conditions v ih = 2.4v v il = 0.4v t r = 5ns t f = 5ns 1.4v c l * 1 = 100pf, 1ttl c l * 1 = 100pf, 1ttl item v cc = 2.7 to 3.6v conditions v ih = 2.2v v il = 0.6v t r = 5ns t f = 5ns 1.4v c l * 1 = 30pf, 1ttl c l * 1 = 100pf, 1ttl v cc = 3.3v 0.3v -10llx -12llx
?5 cxk5t8257btm/bym/bm write cycle time address valid to end of write chip enable to end of write data to write time overlap data hold from write time write pulse width address setup time write recovery time (we) write recovery time (ce) output active from end of write write to output in high z item symbol min. max. min. max. -10llx v cc = 2.7 to 3.6v v cc = 3.3v 0.3v -12llx unit t rc t aa t co t oe t oh t lz t olz t hz * 1 t ohz * 1 100 20 10 10 100 100 50 35 35 120 20 10 10 120 120 60 40 35 min. max. min. max. -10llx -12llx 85 20 10 10 85 85 50 35 35 100 20 10 10 100 100 50 35 35 read cycle time address access time chip enable access time (ce) chip enable to output valid chip hold from address change chip enable to output in low z (ce) output enable to output in low z (oe) chip disable to output in high z (ce) output disable to output in high z (oe) read cycle (we = h? * 1 t hz and t ohz are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. * 2 t whz is defined as the time requied for outputs to turn to high impedance state and is not referred to as output voltage level. write cycle ns item symbol min. max. min. max. -10llx v cc = 2.7 to 3.6v v cc = 3.3v 0.3v -12llx unit t wc t aw t cw t dw t dh t wp t as t wr t wr1 t ow t whz * 2 100 80 80 35 0 60 0 0 0 10 35 120 100 100 50 0 70 0 0 0 10 40 min. max. min. max. -10llx -12llx 85 80 80 35 0 60 0 0 0 10 35 100 80 80 35 0 60 0 0 0 10 35 ns
?6 cxk5t8257btm/bym/bm timing waveform read cycle (1) : ce = oe =v il , we = v ih address t aa t rc t oh data out previous data valid data valid read cycle (2) : we = v ih address t aa t rc t co t lz t hz t ohz t oe t olz ce oe data out high impedance data valid write cycle (1) : we contorl address t aw t wc t cw t as t wp t dh t whz t dw ce we data out high impedance data valid t ow [ * 2 ] [ * 2 ] oe data in t wr [ * 1 ]
?7 cxk5t8257btm/bym/bm write cycle (2) : ce control address oe t wc t aw data valid t as t cw t wr1 t wp t dw t dh high impedance ce we data out data in * 1 write is executed when both ce and we are at low simultaneously. * 2 do not apply the data input voltage of the opposite phase to the output while i/o pin is output condition.
?8 cxk5t8257btm/bym/bm v cc 2.7v 2.2v v dr ce gnd t cdrs data retention mode t r ce 3 v cc ?0.2v data retention waveform low supply voltage data retention waveform data retention voltage data retention current data retention setup time recovery time v dr i ccdr1 i ccdr2 t cdrs t r ce 3 v cc ?0.2v v cc = 2.0 to 3.6v ce 3 v cc ?0.2v chip disable to data retention mode 2 0 5 0.1 0.12 * 1 3.6 6 3 7.0 v ? ns ms item symbol test conditions min. typ. max. unit data retention characteristics (ta = ?5 to +85?) * 1 v cc = 3.3v, ta = 25? v cc = 3.0v ce 3 2.8v ?5 to +85? ?5 to +70? +25?
?9 cxk5t8257btm/bym/bm package outline unit: mm cxk5t8257btm cxk5t8257bym sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy 28pin tsop (plastic) * 8.0 0.1 0.55 0.1 * 11.8 0.1 13.4 0.3 1.2 max 0.5 0.1 0?to 10 0.2 ?0.05 + 0.1 0.05 ?0.05 + 0.1 0.127 ?0.02 + 0.07 a 7 1 28 22 8 21 tsop-28p-l01 tsop028-p-0000-a 0.1 detail a 0.2g note: dimension * ?does not include mold protrusion. sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating copper / 42 alloy 28pin tsop (plastic) * 8.0 0.1 0.55 0.1 * 11.8 0.1 13.4 0.3 1.2 max 0.5 0.1 0.2 ?0.05 + 0.1 0.05 ?0.05 + 0.1 0.127 ?0.02 + 0.07 a 22 28 1 7 21 8 tsop-28p-l01r tsop028-p-0000-b 0.1 0?to 10 detail a 0.2g note: dimension * ?does not include mold protrusion.
?10 cxk5t8257btm/bym/bm cxk5t8257bm sony code eiaj code jedec code package structure package material lead treatment lead material package weight epoxy resin solder plating 42 alloy 28pin sop (plastic) sop-28p-l05 * sop028-p-0450 0.7g m 18.0 ?0.1 + 0.4 0.4 0.1 1.27 8.4 ?0.1 + 0.3 11.8 0.4 0?to 10 0.15 ?0.05 + 0.1 1.0 0.2 0.1 ?0.05 + 0.2 0.15 2.3 ?0.15 + 0.4 15 14 1 28 0.24
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